The present invention relates to a semiconductor memory device. More particularly, the invention relates to a semiconductor memory device and initializing method providing high reliability in set-up data.
Semiconductor memory devices may be generally categorized as volatile or non-volatile in their operative nature. Volatile memory devices access data rapidly, but lose stored data when power is interrupted. In contrast, non-volatile memory devices retain stored data in the absence of applied power.
Non-volatile memory devices include the Mask Read-Only Memory (MROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). It is relatively difficult to write data to MROM, PROM and EPROM devices. Since they do not suffer under this disability, EEPROM devices find increasing acceptance in a variety of applications. So-called flash memory, one type of EEPROM storing one or more data bits per constituent memory cell, is particularly well suited for applications that require large data storage capacity in a highly (or densely) integrated design. NAND-type flash memory is especially capable of being highly integrated, as compared with other types of flash memory.
However, the highly integrated nature of contemporary NAND flash memory results in a corresponding decrease in circuit line width, an increase in the number of related fabrication processes, and an overall increase in the complexity of the final device. These outcomes may cause a decrease in the functional yield of the NAND flash memory devices, or memory cells within same.
In order to improve fabrication yield, certain semiconductor memory devices, not just NAND flash memory, are implemented with one or more extra memory cell, hereafter referred to as redundant memory cell(s). A redundant memory cell may be used to functionally replace a defective memory cell. Accordingly, a memory device incorporating one or more redundant memory cells must include means for converting the address of a defective memory cell into an address that will access a corresponding redundancy memory cell.
When a defective memory cell is detected during device testing, the address of the defective cell is converted into a redundant memory cell address through a series of processes, such as fuse cutting in a fuse box within the memory device. As a result of this memory cell “repair” capability, a relatively small number of defective memory cells will not result in a failed memory device. Consistent with this repair capability, the respective addresses of defective memory cells are stored in a non-volatile memory during device testing. These addresses may then be read upon system initialization (i.e., upon memory device power-up).
Memory system initialization involves a great many processes, such as the definition of various internal voltages. Such voltages are direct current (DC) signals and are usually generated by voltage generator within the memory device. The respective levels of such DC voltages are determined according to optimal (or assumed “standard”) conditions during memory device design, and optimum operation of the memory device is closely related to the proper definition of these levels. However, due to fabrication process or operating condition variations, certain DC voltages generated within the memory device may not correspond to optimal definitions. In order to adjust or “trim” the value of DC voltages to better correspond with defined parameters, so-called DC trimming data may be stored in a non-volatile memory within the memory device. Subsequently, one or more DC voltage(s) may be trimmed according to the DC trimming data which is read during a memory system initialization.
FIG. 1 is a waveform diagram illustrating the change of an internal power voltage generated within a semiconductor memory device upon system initialization. Referring to FIG. 1, system initialization for the memory device generally begins before the internal power voltage VDD reaches a defined voltage level of V2. That is, the memory device may begin initialization (e.g., execute a Power-On Reset (POR) operation) when the internal power voltage VDD reaches a threshold voltage V1 which is less than the defined voltage V2.
Once memory system initialization begins, set-up data is read from an initialization memory (e.g., an assigned portion of the greater memory cell array for the memory device), and repair operations directed to defective memory cells and/or a trimming operations directed to various DC voltages may be performed in accordance with the set-up data. Unfortunately, the set-up data is read before the internal power voltage VDD stabilizes at its defined level V2. The set-up data is also read before critical DC voltages are trimmed in accordance with trimming data stored as part of the set-up data. Thus, it is highly possible for one or more data read errors to happen when the set-up data is read during system initialization. Apart from the level of certain applied voltages, some memory cells in the initialization memory may be defective. From such defective memory cells, one or more errors may be included in the set-up data resulting in reduced reliability of the memory device.